1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which includes a plurality of input/output circuits and more particularly to an improvement in an output DC offset of a read circuit in a magnetic read/write circuit.
2. Description of the Background Art
FIG. 4 shows an example of conventional magnetic read/write circuits. Both ends of a head 2 are connected to the collectors of write transistors Q.sub.1W and Q.sub.2W through terminals P1 and P2, respectively. Similarly, both ends of a head 3 are connected to the collectors of write transistors Q.sub.3W and Q.sub.4W through terminals P3 and P4, respectively. The center taps of the heads 2 and 3 are connected to a power source 1. The bases of read transistors Q.sub.1R and Q.sub.2R are connected to the collectors of the write transistors Q.sub.1W and Q.sub.2W, respectively. Similarly, the bases of read transistors Q.sub.3R and Q.sub.4R are connected to the collectors of the write transistors Q.sub.3W and Q.sub.4W, respectively. The emitters of the write transistors Q.sub.1W to Q.sub.4W are connected in common and are grounded through a write current source 8. The bases of the write transistors Q.sub.1W to Q.sub.4W are equipped with terminals 4 to 7, respectively.
The collectors of the read transistors Q.sub.1R and Q.sub.3R are connected in common to a power source 9 through a load circuit 10. Similarly, the collectors of the read transistors Q.sub.2R and Q.sub.4R are connected in common to the power source 9 through the load circuit 10.
The differential pair outputted from the load circuit 10 is inputted to an output amplifier 17 through lines 15 and 16. The differential pair outputted from the amplifier 17 is inputted to terminals 18 and 19.
The emitters of the read transistors Q.sub.1R and Q.sub.2R are connected in common to a read current source 13 through a switch 11. Similarly, the emitters of the read transistors Q.sub.3R and Q.sub.4R are connected in common to the read current source 13 through a switch 12.
A switch circuit 14 performs read/write switching. Outputs 20 and 21 of the switch circuit 14 are complementary signals. That is, the read current source 13 is on and the write current source 8 is off in a read operation. The read current source 13 is off and the write current source 8 is on in a write operation.
A block HDn operates when the head 2 is selected, and a block HD(n+1) operates when the head 3 is selected. The block HDn includes the write transistors Q.sub.1W and Q.sub.2W, the read transistors Q.sub.1R and Q.sub.2R and the terminals P1 and P2. The block HD(n+1) similarly includes the write transistors Q.sub.3W and Q.sub.4W, the read transistors Q.sub.3R and Q.sub.4R and the terminals P3 and P4.
There is shown in FIG. 2 an arrangement of the blocks HDn and HD(n+1) on the semiconductor integrated circuit. The terminals P1 to P4 are provided in the form of wiring pads P11 to P14 for connection to the heads on the semiconductor integrated circuit. Another arrangement is shown in FIG. 3, in which the read transistors and write transistors are transposed.
The operation of the magnetic read/write circuit of FIG. 4 will be discussed below. When the head 2 is selected for the write operation, the block HDn is selected. Specifically, the write transistors Q.sub.1W and Q.sub.2W are turned on by the current fed to the terminals 4 and 5, and the switch 11 is turned on. The read current source 13 is turned off and the write current source 8 is turned on by the switch circuit 14 with the output 20, 21 respectively. This permits a write current to flow in the write transistors Q.sub.1W and Q.sub.2W, so that a magnetic field is generated in the head 2. The magnetic write operation is thus performed on a medium not shown.
Following is the operation of reading information which has been put on the medium. The read current source 13 is turned on and the write current source 8 is turned off by the switch circuit 14 with the output 20, 21 respectively. The signal which is read out of the head 2 is applied to the bases of the read transistors Q.sub.1R and Q.sub.2R to be differentially amplified. The amplified signals are sent to the load circuit 10, pass through the lines 15 and 16, and are outputted to the terminals 18 and 19 by the amplifier 17. The same is true for the operation in the block HD(n+1) when the head 3 is selected.
While the head 2 is selected, the block HD(n+1) which controls the head 3 does not operate for the reason described below. Since no current is fed to the terminals 6 and 7, the write transistors Q.sub.3W and Q.sub.4W do not operate even when the write current source 8 is on. Since the switch 12 is off, the read transistors Q.sub.3R and Q.sub.4R do not operate.
Hereinafter described is the read operation by selecting the head 3 after the write operation by means of the head 2 and the subsequent read operation. FIG. 5 shows the sequence of the aforesaid operation in the magnetic read/write circuit of FIG. 4. In a read/write switching operation W/G, the region W indicates a write time period, and the region R indicates a read time period. In a head switching operation HS, the regions Sn and S(n+1) indicate the selection of the blocks HDn and HD(n+1), respectively. An offset V.sub.off indicates the DC offset of the differential pair outputted from the terminals 18 and 19.
Until time t.sub.1, the head 2, i.e., the block HDn is selected, and the write operation is performed. When the operation is switched from write to read at time t.sub.1, a slight offset voltage difference V.sub.1 is generated. The offset voltage difference V.sub.1 results from an asymmetry layout of the read transistors Q.sub.1R and Q.sub.2R, and can be normally minimized.
When the head 3, i.e., the block HD(n+1) is selected at time t.sub.2 with the read operation continued, an offset voltage difference V.sub.2 is generated. The offset voltage difference V.sub.2 results from an asymmetry operation of the read transistors Q.sub.3R and Q.sub.4R affected by heat generated in the write transistors Q.sub.1W and Q.sub.2W which have been in operation before time t.sub.1. The offset voltage difference V.sub.2 is larger than the offset voltage difference V.sub.1.
Since the output signal of the amplifier 17 is normally inputted to the next circuit by capacitance coupling, the offset voltage differences V.sub.1 and V.sub.2 are preferably small. For this purpose, it is preferable that the heat generated in the write transistors Q.sub.1W and Q.sub.2W has no effect or uniform effects on the read transistors Q.sub.1R to Q.sub.4 R.
In the conventional blocks HDn and HD(n+1 ), however, the transistors and wiring pads are disposed adjacent to each other as shown in FIGS. 2 and 3. The read transistors Q.sub.1R to Q.sub.4R are very susceptible to the heat generated in the write transistors Q.sub.1W and Q.sub.2W.
With reference to FIGS. 2 and 3, the read transistors Q.sub.1R and Q.sub.2R are arranged in symmetrical relation to the write transistors Q.sub.1W and Q.sub.2W. Accordingly, the read transistors Q.sub.1R and Q.sub.2R are affected symmetrically by the heat generated in the write transistors Q.sub.1W and Q.sub.2W, so that the offset voltage difference V.sub.1 can be minimized.
On the other hand, it is difficult to arrange the read transistors Q.sub.3R and Q.sub.4R, which are included in the other block, in symmetrical relation to the write transistors Q.sub.1W and Q.sub.2W. For reduction of the offset voltage difference V.sub.2, it is necessary to space the read transistors Q.sub.3R and Q.sub.4R apart from the write transistors Q.sub.1W and Q.sub.2W. It is, however, not preferable to increase the area of the blocks HDn and HD(n+1) from the viewpoint of integration. In other words, it is difficult to minimize the offset voltage difference V.sub.2 relative to the predetermined area of the blocks.
In the conventional semiconductor integrated circuit including the magnetic read/write circuit, since the heat generated in the write transistors has unbalanced influences on the read transistors, there has been a problem that a large offset voltage difference is generated before and after the head switching operation when the heads are switched to perform the read operation immediately after the write operation.